When compiling a DDR2 hard memory controller (HMC) in Quartus II v13.1, a Critical Warning occurs during timing analysis. Is it okay to ignore it?

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When I compile the DDR2 Hard Memory Controller (HMC) in Quartus II v13.1, I get a Critical Warning in the timing analysis. can i ignore it?

Critical Warning: Timing analysis was performed on core ddr2_core_example_if0_p0 using Quartus II v13.1 with a preliminary timing model and constraints. You must regenerate this IP in a future version of Quartus II to update the timing constraints to match the timing model.

Category: External memory interface
Tools: Quartus® II
Device: Cyclone® V

You can safely ignore this Critical Warning.
Altera has confirmed that there is no problem with this Critical Warning.

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