When using the SoC's Accelerator Coherency Port (ACP), what settings are required in addition to the ACP ID Mapper settings?

Narrow down by specifying conditions

There are currently 4332 hits.

When using the Accelerator Coherency Port (ACP) of the SoC, what settings are required other than the ACP ID Mapper settings?

SoC FPGAs

Tools: SoC Embedded Design Suite (SoC EDS)
Device: Cyclone® V

When using ACP, the following two settings are required.
It seems that the SMP bit has already been set, so please add the contents of "Initializing the SCU (Snoop Control Unit)" below.

・Initialize SCU (Snoop Control Unit) Implement the following processing near the start of main
-------------------------------------------------- -----------------
SOCFPGA5XS1_BSP_SCU_CTLR = 0x0; /* Disable SCU */
SOCFPGA5XS1_BSP_SCU_INV_WAY = 0xFFFF; /* Invalidate SCU Tag RAM */
SOCFPGA5XS1_BSP_SCU_CTLR = 0x1; /* Enable SCU */
-------------------------------------------------- -----------------

・Set SMP bit of ACTLR (Auxiliary Control Register) to ON
-------------------------------------------------- -----------------
MRC p15,0,r1,c1,c0,1
ORR r1, r1, #0x40
MCR p15,0,r1,c1,c0,1
-------------------------------------------------- -----------------

Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.

Inquiry form

Site Search