Category: Specifications
Tools: Quartus® II
Device: Stratix® IV


Support for 100 Ω On-Chip Termination (On-Chip Termination/Rd) inside the FPGA on differential input pins in Stratix IV devices is as follows:

• I/O pins in Row (Left & Right) I/O banks and dedicated clock input pins (CLK[0, 2, 9, 11]) are supported
• Column (Top & Bottom) I/O bank I/O pins and dedicated clock input pins (CLK[1, 3, 8, 10]) and corner PLL clock input pins are not supported

When constraining, in the Assignment Editor,

To: <input pin>
Assignment Name: Input Termination
Value: Differential

Please compile with the following restrictions.
After compiling, check that Termination is set to Differential in Fitter ⇒ Resource Section ⇒ Input Pins in the compilation report.

For details, please refer to the document below.
https://www.altera.com/en_US/pdfs/literature/hb/stratix-iv/stx4_siv51008.pdf
(Search for "Differential I/O Termination".)