I am considering adjusting the waveform of a DDR3 memory interface. On the DDR3 side, the input and output can be adjusted by changing the values when generating the IP, but looking at the specifications on the FPGA side, the values appear to be fixed. (For example, only 50Ω for SSTL-15 Class1.) Is it possible to change this termination resistance value?

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I'm looking into waveform tuning for a DDR3 memory interface. The input and output on the DDR3 side can be adjusted by changing the numerical values when generating the IP, but on the FPGA side it looks like a fixed value as far as the specifications are concerned. (Example: Only 50Ω for SSTL-15 Class1.) Is it possible to change this termination resistance value?

The termination resistance value is fixed for each I/O Standard, so the termination resistance value cannot be changed. Please refer to the Device Handbook of each device family for the termination resistance value.

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