I am evaluating PCIe Endport using Altera's Cyclone V SoC Development Kit RevC. At that time, there are differences in the Link up status depending on whether or not SSC is set on the Host side. Is there any possible cause?

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Using Altera's Cyclone V SoC Development Kit RevC, PCIe Endport is being evaluated. At that time, there is a difference in the link up situation depending on whether or not the SSC is set on the host side. Any ideas what could be the cause?

PCI Express

When using Altera's Cyclone V SoC Development Kit, it is necessary to change the connection on the board of the PCIe Ref Clk part.

Used as Root Port => Connect R253, R254, R249, R251 (Default connection)
Used as End Point => Remove above resistor and connect R250 and R252

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