Intel: When configuring an interface for SSTL-15 Class I on Arria V devices, how should the oct pin of the Hard Memory Controller be handled?
Tools: Quartus® II
Device: Arria® V
The termination resistance of the oct_rzq pin in Arria V devices varies by design, so you need to determine whether it is 100Ω or 240Ω by comparing the resistance values in the device handbook below and the Assignment Editor.
https://www.altera.com/en_US/pdfs/literature/hb/arria-v/av_5v2.pdf
* See "On-Chip I/O Termination in Arria V Devices".
(example)
For DQ / DQS, I/O Standard = SSTL-15 Class I / Differential 1.5-V SSTL Class I Given "Series/Parallel 50 Ohm with Calibration" pin constraints, Table 5 in the above device handbook Referring to -21 ,
Series OCT is RS
Parallel OCT is RT
are referred to.
Referring to Tables 5-23 and 5-24, the external resistance value of RZQ at all applicable locations is "100Ω".
*
Even if the internal resistance value of OCT can be set to either 25Ω or 50Ω, 50Ω will be set as the default setting when constraints such as I/O Standard and OCT are given by pin_assignment.tcl.
This resistance value can be changed depending on the specifications, but in many cases 50Ω is used as it is.
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