The clock pins that input to the HPS of Cyclone V SoC are listed as EOSC1 and EOSC2 in the Cyclone V Device Handbook, but I cannot find them in the Quartus II Pin Planner.

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Cyclone V SoC's HPS clock pins are described as EOSC1 and EOSC2 in the Cyclone V Device Handbook, but I can't find them in the Quartus II Pin Planner.

SoC FPGAs

Pins listed in device handbooks have the following names in the Quartus II and Pin Connection Guidelines.

EOSC1 = HPS_CLK1
EOSC2 = HPS_CLK2

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