Error (175020): Illegal constraint of PLL output counter to the region (X, Y) to (X, Y): no valid locations in region
Error (177013): Cannot route from the PLL output counter output to destination dual-regional clock driver because the destination is in the wrong region

Tools: Quartus® II


It is believed that this happened because the Dual Regional Clock did not own a specific location, but tried to place it in that location.
In the QSF file or Assignment Editor, change the Global Signal settings for the clock signals below from Dual-Regional Clock to Regional Clock.

・pll_avl_clk
・ pll_config_clk
- pll_addr_cmd_clk

For details, please refer to the following Knowledge Database (KDB).
 https://www.altera.com/support/support-resources/knowledge-base/solutions/rd03312013_521.html