I have enabled the HPS PLL output as a user clock from the settings on the HPS Clock tab of Qsys HPS, but it is not output at the set frequency. Please tell me what to do.

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I have enabled the HPS PLL output as the user clock from the HPS Clock tab settings in Qsys HPS, but it does not output at the set frequency. Please tell me what to do.

Platform Designer SoC FPGA Clock/PLL

Target Version: Quartus II v13.0 / v13.0 SP1 / v13.1

This is because the PLL frequency setting is performed with the default settings that the Preloader has.
Therefore, to set any frequency, you need to manually modify the Preloader source code.

The modified parts in the Preloader source code are as follows.
(Preloader SRC)\uboot-socfpga\board\altera\socfpga_cyclone5\pll_config.h

- #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15)
- #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9)
- #define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)

[Reference link]
http://www.rocketboards.org/foswiki/Documentation/PreloaderClockingCustomization

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