The f2h_sdram0_data port is not accessible from the FPGA fabric. Are there any settings required?

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I cannot access the f2h_sdram0_data port from the FPGA fabric. Are there any settings required?

SoC FPGA SoC EDS/DS-5 Quartus Prime Platform Designer

No special settings are required.
However, access to the f2h_sdram0_data port from the FPGA fabric is supported starting with Quartus II v13.0SP1.

If you have generated your system with an older version, please regenerate with Qsys for Quartus II v13.0SP1 or later and recompile your design. Note that you should also regenerate the Preloader using the handoff file generated above.
Also, to use this port, it is necessary to reset and enable the bridge after FPGA configuration is complete.

Please also refer to the URL link below.
http://www.rocketboards.org/foswiki/Documentation/GSRDProgrammingFPGA

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