External Flash ROM (data width: 32bit) installed in Stratix V GX FPGA development kit

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External Flash ROM mounted on Stratix V GX FPGA development kit (data width: 32bit)

By default, the PFL design is in FPGA Configuration mode, so it is not visible.

In order to display the Flash ROM in the Quartus II Programmer, it is necessary to change the PFL design.

How to change is shown below.

	1.	Download and install the .exe from the "kit installation" of the URL link below
	2.	Start max5.qpf in <installation folder>\stratixVGX_5sgxea7kf40_fpga\examples\max5\max5_s5_prod_13_0_0 with Quartus II
	3.	Double-click max5 => pfl_control:pfl_control_inst => p2:pfl_x32_inst from Project Navigator to launch Parallel Flash loader MegaWizard
	4.	Change What operating mode will used? in General tab to "Flash programming and FPGA Configuration" and regenerate Parallel Flash Loader core

	5.	Compile this project after generation
	6.	Write generated pof to MAX V device
	7.	Flash ROM is displayed when Auto Detect of Programmer is executed

Stratix V GX FPGA Development Kit Information
　https://www.altera.co.jp/products/boards_and_kits/dev-kits/altera/kit-sv-gx-host.html

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