The reason why it is not assigned to a memory block is that the HDL design is recognized as not a memory design.

By making the following two settings, you may assign to a memory block.

1: Add attribute descriptions in your HDL design
・For Verilog HDL
/* synthesis ramstyle = "memory type" */;
・For VHDL
attribute ramstyle : string;
attribute ramstyle of memory design name : signal is "memory type";

For detailed description method, please refer to the following URL link.

  Verilog-HDL
    https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vlog/vlog_file_dir_ram.htm

VHDL
    https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/vhdl/vhdl_file_dir_ram.htm

2: Specify to replace the design with memory in the Assignment Editor

Select Assignments ⇒ Assignment Editor
・Register memory design in To
・Set Assignment Name to Auto RAM Replacement or Auto ROM Replacement
・Set Value to On
・Set Enable to Yes

* When registering a memory design to Assignment Editor, it is easier to do so from Project Navigator.