Is it necessary to write the timing (frequency) of the clock generated by the PLL generated by ALTPLL in the SDC?

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Is it necessary to describe the timing (frequency) of the generated clock in the SDC for the PLL generated by ALTPLL?

Clock/PLL Timing Constraint/Analysis Quartus Prime

If you use the MegaWizard Plug-In Manager to generate your PLL design, you must still include the clock constraints in the SDC file.

This applies to the "create_clock" command to set the reference clock for the PLL, and the "derive_pll_clocks" command to derive output clocks from the PLL design.
However, there is information that Cyclone V, Arria V, and Stratix V are not constrained correctly when clock switchover is included.

For details, please check the URL below.
https://www.intel.com/content/www/us/en/support/programmable/articles/000078521.html

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