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I'm considering PS configuration on Cyclone IV E, is it okay for the DCLK pin to toggle after the FPGA is in user mode?
It does not matter if the DCLK pin is toggling after the FPGA enters user mode.
Please refer to the device handbook below for details.
https://www.altera.com/en_US/pdfs/literature/hb/cyclone-iv/cyiv-51008.pdf
In passive schemes, you cannot use DCLK as a user I/O in user mode.
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