As a result of IBIS simulation, better results were obtained with IO settings different from those set in Quartus II. Please tell me how to apply this result to Quartus II.

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IBIS simulations have shown better results with different IO settings than the one set in Quartus II. How can I apply this result to Quartus II?

Board Simulation Quartus Prime

Let's take the DDR3 clock as an example.

I set it to dsstl15i_crio_r50s1 in Quartus II and ran compilation. However, in the IBIS simulation, the dsstl15i_crio_d8s1 setting gave the best waveform, so I decided to change the Quartus II setting.

IO model names are named according to the following rules.

	dsstl15i	- Differential 1.5V SSTL Class I
	sstl15i	- 1.5V SSTL Class I
	crin	- Column input, DIFFIO_RX pin
	d8	- 8mA Current Strength
	d6	- 6mA Current Strength
	r50	- 50 Ohm series on-chip termination without calibration
	r50c	- 50 Ohm series on-chip termination with calibration
	s1	-fast Slew Rate

For example dsstl15i_crio_d8s1 is

1)	dsstl15i	- Differential 1.5V SSTL Class I
2)	sstl15i	- 1.5V SSTL Class I
3)	d8	- 8mA Current Strength
4)	s1	-fast Slew Rate

It means that it contains elements of

In Quartus II you have to set

	A)	Differential 1.5V SSTL Class I No change required
	B)	Column input and DIFFIO_RX pin are already pinned, so no need to change
	C)	Change Current Strength to 8mA
	D)	Slew Rate is Default and Fast (set value is 1), so no need to change
	E)	Removed the 50 Ohm series on-chip Termination without Calibration setting as the r50 element is gone

becomes.

Essentially in this example
・ Delete the setting of 50 Ohm series on-chip Termination without Calibration
・ Added setting of 8mA for Current Strength
It will be the work of

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