An error occurs when monitoring rx_in of Megafunction Name(s): ALTLVDS_RX (LVDS Receiver macro) in SignalTap II Logic Analyzer. The FPGA is Stratix IV.

Narrow down by specifying conditions

There are currently 4332 hits.

In the SignalTap II Logic Analyzer, I get an error when I monitor rx_in for Megafunction Name(s) : ALTLVDS_RX (LVDS Receiver macro). The FPGA is a Stratix IV.

<error message>
Error (15118): datain port of HSDI receiver atom "rx_0" must be fed by input pin that does not feed any other logic

This is because other logic cannot be connected to the data input pin (rx_in: serial data side) of ALTLVDS_RX.
(By setting SignalTap II, other logic is connected to the data input pin)

As a workaround for this problem, it is possible to check the data without directly monitoring rx_in by sampling the data (rx_out) output from ALTLVDS_RX with the synchronous clock rx_outclock and monitoring it with SignalTap II.

Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.

Inquiry form

Site Search