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LVDS receive on Arria V devices. Is it possible to enable Input Termination if a parallel clock is assigned to the clock input pin?

Clock/PLL

LVDS receive on Arria V devices. Is it possible to enable Input Termination if a parallel clock is assigned to the clock input pin?

Yes. It is possible.

In Arria V devices, you can enable internal termination resistors for the LVDS parallel clock input (rx_inclock).

To enable the internal termination of LVDS_RX, set "Input Termination = Differential" in Assignment Editor and compile.

After compiling, check the compilation report to see that internal termination is enabled.

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