Is it okay to connect the clock driven from the PLL inside the FPGA to the core clock input of the DDR2 SDRAM Controller?

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There are currently 4332 hits.

Can I connect the clock driven from the PLL inside the FPGA to the core clock input of the DDR2 SDRAM Controller?

IP clock/PLL

No.

DDR2/DDR3 SDRAM Controller uses PLL by default.
In your question's configuration, the PLLs will be cascaded.

Depending on the layout, Quartus II Fitting may pass, but a Critical Warning will occur.
In addition, it is necessary to take care such as clock jitter, control until the previous stage PLL locks, and countermeasures when lock is lost, so please use a configuration that does not cascade as much as possible.

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