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Intel: Looking at the Parallel Flash Loader Megafunction User Guaid (PFL), I see an external pull-up resistor on the nCONFIG pin, why?
In the Parallel Flash Loader circuit using CPLD devices, the fpga_nconfig pin is OpenDrain, so connecting an external pull-up resistor is mandatory.
The PS configuration circuit in the Device Handbook does not mention an external pull-up resistor because the device controlling configuration is not necessarily a CPLD.
For details, please refer to the following URL link, page52, fpga_nconfig item of Table 14. PFL Signals (Part 2 of 4).
https://www.altera.com/en_US/pdfs/literature/ug/ug_pfl.pdf
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