In the Frequency/PLL setting tab of ALTLVDS_TX, there is a setting called "What is the phase alignment of tx_in with respect to the rising edge of tx_inclock?". What should I consider when setting this phase?

Narrow down by specifying conditions

There are currently 4342 results.

There is a setting "What is the phase alignment of tx_in with respect to the rising edge of tx_inclock?" in the Frequency/PLL setting tab of ALTLVDS_TX. How should this phase be set?

tx_in is transferred from tx_inclock to tx_coreclock inside ALTLVDS_TX.
If a timing violation occurs due to this clock crossover, please adjust this phase to avoid the timing violation.

Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.

Inquiry form

Site Search