What does Quartus II do when compiling a design that has port declarations for input, output, and bidirectional pins that are not connected to anything?

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What does Quartus II do if I compile a design with port declarations for inputs, outputs, and bidirectional pins that are not connected anywhere?

Each pin attribute is shown.

For INPUT
Input attribute, internal unconnected

For OUTPUT
Output attribute, fixed to VCC or GND

For BIDIR
output side
OPEN DRAIN (OE is Disable)
input side
Input attribute similar to INPUT, internal unconnected

Be sure to check the warning message in the compilation report and the Netlist Viewer function (RTL Viewer, Technology Map Viewer) to see how it was handled.

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