After making changes in Chip Planner, when I executed Check and Save All Netlist Changes, a warning occurred. Please tell me how to resolve it.

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After making changes in Chip Planner, I ran Check and Save All Netlist Changes and got a warning. Please tell me how to resolve it.

Quartus Prime

<Warning message>
Warning: Timing-driven compilation is disabled - timing performance will not be optimized

This occurs because timing-driven compilation is not enabled when ECO (Engineering Change Order) is executed.

The problem can be solved by changing the settings as shown below.
1. Select Assignments ⇒ Settings
2. Select Fitter Settings ⇒ More Settings
3. From Existing option settings, set Optimize Timing for ECOs to "ON"

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