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In the ALTLVDS setting, there is Use Shared PLL (s) for receivers and transmitters, but if this setting is ON and the PLL is shared, are there any restrictions?

IP clock/PLL

The following clock constraints arise:
・ Serial clock for transmission and reception (for serial-parallel conversion)
・ Parallel clock for transmission and reception
must be the same.

The number of LVDS channels can be different for transmit and receive.

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