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The create_generated_clock is easily constrained in the GUI with sdc constraints on the output of the PLL, is there an easier way?
Quartus Prime
Timing Constraints/Analysis
Clock/PLL
When you load an sdc with a derive_pll_clocks command, the messages window displays the sdc descriptions of the PLL outputs recognized by derive_pll_clocks. Copy this, edit the necessary parts, and paste it into the sdc description.
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