I would like to configure LVPECL input/output using FPGA. Is it possible?

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Is it possible to configure LVPECL input/output with FPGA?

Below is the LVPECL correspondence table classified by device family.

Device	input	output
Stratix II	○	○
Stratix III	○	×
Stratix IV	○	×
Stratix V	○	×
Arria	○	×
Arria II	○	×
Cyclone II	○	×
Cyclone III	○	×
Cyclone IV	○	×
Cyclone V	○	×

Only Stratix II devices support input/output, but transfer speeds are limited to 450MHz.

For detailed specifications, search for "LVPECL" in each Device Handbook.

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