You need to set the "GXB 0 PPM Core Clock Setting" in the Quartus II Assignment Editor.

When the parallel clock (tx_coreclk) on the transmission side is enabled on the ALTGX MegaCore, the clock must have no frequency deviation from the parallel (low speed) clock inside the ALTGX.

Inside the high-speed transceiver channel is a TX phase compensation FIFO, and the incoming parallel clock is used as the write clock for that FIFO. Also, the parallel clock inside the transceiver channel is used as the read clock for this FIFO. If there is a frequency deviation between the write clock and read clock, the FIFO will be destroyed and data transfer will not be performed correctly. You also need to specify that designation for Quartus II on the Assignment Editor.
If not specified, the Quartus II will generate a compilation error.

For details, refer to the handbook of each device.

Example: Stratix IV GX device reference page
  https://www.altera.com/en_US/pdfs/literature/hb/stratix-iv/stx4_siv52001.pdf
P1-14 TX Phase Compensation FIFO

  https://www.altera.com/en_US/pdfs/literature/hb/stratix-iv/stx4_siv52002.pdf
P2-51 FPGA Fabric-Transmitter Interface Clocking
P2-60 Table 2–16. Quartus II Assignments