I mistakenly connected [0:4] to [4:0] in the PCIe lane wiring on the board in the FPGA implementation board using the PCI Express hard IP. Can it be solved without modifying the board?

When using the PCI Express hard IP, there is a Lane Reversal function, so there is no need to modify the board.
Lane Reversal is valid not only for x4 but also for x1, x2 and x8.

Please note that the Lane Reversal feature is not supported for PCI Express soft IP.

For details of Lane Reserval, please refer to the document at the URL link below.
PCI Express megafunction user guide (page 201: Lane Initialization and Reversal)
    https://www.altera.com/en_US/pdfs/literature/ug/ug_pci_express.pdf