When selecting and using multiple clock sources, is a structure that uses combinational logic for selection the best?

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When selecting and using multiple clock sources, is a structure that selects with combinatorial logic the best?

Clock/PLL

If the clock signal is selected by a combinational circuit, the signal quality may be degraded or a delay may occur.
Therefore, when selecting a clock, we recommend using the dedicated clock selector built into the FPGA. This clock selector is available by selecting ALTCLKCTRL in the MegaWizard Plug-In Manager.

Please refer to the document at the following URL link for the usage and specifications of the clock selector.
The description method in Verilog HDL is also described in the URL link below.
　https://www.altera.com/en_US/pdfs/literature/ug/ug_altclock.pdf

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