Please tell me about ALTCLKCTRL megafuncion. With Stratix III, I would like to output one clock selected from five clock systems, but there are only up to 4to1. In this case, is it possible to use two stages of 3to1 design?

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Tell me about the ALTCLKCTRL megafuncion. I want to output 1 clock selected from 5 clocks on the Stratix III, but there are only up to 4to1. In this case, is it possible to use two stages of the 3to1 design?

IP clock/PLL

This configuration is not possible because the output of ALTCLKCTRL cannot be connected to the input of a subsequent ALTCLKCTRL.

The reason is that out of the four ATLCLKCTRL inputs, two are from the P-channel dedicated clock input pins and two are from the PLL.

For details, please refer to the Handbook at the URL link below and search for the keyword “ALTCLKCTRL”.
https://www.altera.com/en_US/pdfs/literature/hb/stx3/stratix3_handbook.pdf

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