Intel: Used the Quartus II MegaWizard Plug-In Manager to generate a RAM design with asynchronous clear (aclr). I put a '1' in the asynchronous clear with a one-shot pulse, but the contents of the RAM are not cleared to '0'

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Intel: I used the Quartus II MegaWizard Plug-In Manager to generate a RAM design with asynchronous clear (aclr). I put a '1' in the asynchronous clear with a one-shot pulse, but the contents of the RAM are not cleared to '0'

The aclr signal in a RAM design is not a signal to clear the RAM, but a signal to clear the registers embedded in the input and output ports.

Data, wren, address, q, byteena_a, etc. are related, but the related ports differ depending on the selected device and generated RAM design, so refer to 'Asynchronous Clear' (page 3- 13).

Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ram_rom.pdf

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