When I select XAUI Mode of ALTGX on Cyclone IV GX, 3 pins like ~reserved_gnd_E1, ~reserved_gnd_E2, and ~reserved_gnd_D4 appear, but what are these?

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When I select XAUI Mode of ALTGX on Cyclone IV GX, 3 pins come out like ~reserved_gnd_E1, ~reserved_gnd_E2, ~reserved_gnd_D4, what is this?

To improve Jitter Performance and BER in the Cyclone IV GX, there is a Quartus II limitation that drops pins around the Transceiver's reference clock (*) to GND when designed at transfer rates of 2.97 Gbps or higher.

For details, please refer to Cyclone IV Device Pin Connection Guideline, P.10 at the URL link below.
https://www.altera.com/en_US/pdfs/literature/dp/cyclone-iv/pcg-01008.pdf

Therefore, please check if it is dropped on the GND plane on the board.
Also, please note that this ~reserved_gnd_xxx varies depending on the transceiver block (REFCLK) used.

(*) Not placed close on the device package, but close on the die.

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