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I created multiple PLLs, but when I look at the compilation report, the number of PLLs used is less than the number of designs. There is no problem in actual operation, but why?

Quartus Prime Clock/PLL

Quartus II compiles with the idea that logic can be realized with as few resources as possible. This feature infers that the PLLs have been merged (logically compressed) during the logical compression process.

There is also a method not to logically compress the PLL when compiling.
For the setting method,
Select Settings... from Assignments
Select Fitter from Category: and click More Settings
Set Auto PLL Merge to OFF and click OK

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