Stratix IV has several Clock input pins, but do they all have the same functionality?

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The Stratix IV has several Clock input pins, are they all the same function?

Each pin supports different functions.

Please check the differences in specifications below.

Stratix IV clock input pin

pin name	clock input	other than clock	when not in use	Single-ended input	Supports differential input	Differential OCT
CLK[1,3,8,10]p	OK	input only	GND	OK	Connect P channel	External
CLK[1,3,8,10]n	Connect N channel
CLK[0,2,9,11]p	User I/O	Quartus II unused of pin setting dependent upon	Connect P channel	OCT Rd
CLK[0,2,9,11]n	Connect N channel
CLK[4:7,12:15]p	Connect P channel	External
CLK[4:7,12:15]n	Connect N channel
PLL_[L1,L4,R1,R4]_CLKp	input only	GND	Connect P channel
PLL_[L1,L4,R1,R4]_CLKn	Connect N channel

Also, during actual design, be sure to check the Pin Connection Guideline at the URL link below.

https://www.altera.com/en_US/pdfs/literature/dp/stratix4/pcg-01005.pdf

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