Intel: Is there a way (setting) to name the wires and registers in the design and leave them uncompressed during logic synthesis?

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Intel: Is there a way (setting) to name Wires and Registers in the design and leave them uncompressed in logic synthesis?

Quartus Prime

Yes, you can set the Quartus II to preserve wire names and register names.

The setting method is shown below.
From the Quartus II menu, select Assignments ⇒ Assignments Editor
in the Assignment Name field
・ Implement as Output of Logic Cell : Retain wire name
・ Preserve Registers : Preserve register names
register and compile

For details, refer to the Quartus II Handbook at the URL link below and search for keywords "Preserve Registers" and "Implement as Output of Logic Cell".
　https://www.altera.com/en_US/pdfs/literature/hb/qts/qts_qii51008.pdf

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