In a design that uses the transceiver of the Hard IP of Cyclone IV GX (e.g. PCI Express Compiler), is it okay to connect a clock that is internally divided (multiplied) to refclk?

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In a design using the Cyclone IV GX Hard IP transceiver (eg PCI Express Compiler), can I connect an internally divided (multiplied) clock to refclk?

PCI Express clock/PLL

In a design using the Cyclone IV GX Hard IP transceiver (eg PCI Express Compiler), can I connect an internally divided (multiplied) clock to refclk?

No, I can not.

refclk should be connected directly from the clock input pin.

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