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When using Altera's PCI-Express hard IP to issue a legacy interrupt (INTA) from inside the FPGA, how long does it take for the interrupt to be notified to the root complex side?
The PCI-Express hard IP issues legacy interrupts by asserting the app_int_sts signal.
In simulation, it takes about 52 clocks (125 MHz = 8 ns cycle) from asserting the app_int_sts signal (Low ⇒ Hi) to outputting an interrupt message, and deasserting the app_int_sts signal (Hi ⇒ Low ) until the interrupt release message is output is about 51 clocks.
It may increase slightly due to differences in hardware latency depending on the device and the degree of transfer congestion at that time, but approximately 50 clocks should be used as a guideline.
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