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When using Altera's PCI-Express hard IP to issue an MSI interrupt from inside the FPGA, how long does it take for the interrupt to be notified to the root complex side?
The PCI-Express hard IP issues legacy interrupts by asserting the app_msi_req signal.
According to simulation, the time from asserting the app_msi_req signal (Low ⇒ Hi) to outputting the interrupt message was about 30 clocks (125 MHz = 8 ns cycle).
It may increase slightly depending on the difference in hardware latency depending on the device and the degree of transfer congestion at that time, but please use about 30 clocks as a guideline.
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