For high-speed LVDS interfacing with Dynamic Phase Alignment (DPA) in Stratix III/IV devices, the Enable PLL calibration feature can be enabled/disabled within the ALTLVDS_RX megacore, but should it be enabled? ?

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When doing high-speed LVDS interfacing with Dynamic Phase Alignment (DPA) on Stratix III/IV devices, you can choose to enable/disable the Enable PLL calibration feature within the ALTLVDS_RX megacore, should it be enabled? ?

Clock/PLL

We recommend enabling it on Stratix III / Stratix IV ES devices.
Stratix IV production devices do not need to be enabled.

An errata has been reported stating that data cannot be received correctly (data misalignment) when using DPA on Stratix III / Stratix IV ES devices.
The PLL calibration function is an effective function to avoid this data misalignment.

When the PLL calibration function is enabled, it is necessary to run a special initialization sequence after releasing reset.

For details, refer to the corresponding page in the Device Handbook of each device.

For Stratix IV devices

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-iv/stx4_siv54001.pdf
See P1-53, Table 1-41.

For Stratix III devices

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stx3/stx3_siii52001.pdf
Please refer to P1-23 and Table1-26.

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