The global_reset_n reset signal resets registers, PLLs, etc. in the High Performance Controller.

When this reset signal is asserted (High => Low), it is reset, and when it is deasserted (Low => High), the controller performs re-calibration.
(Calibration is a function that corrects the strobe signal (DQS) according to the skew between the data bus (DQ) between DDR/DDR2 and FPGA.)

The controller can be used after calibration, but there is a signal "local_init_done" to determine this. (The controller can be used when it goes High.)

For details, refer to the URL link "DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Guide" and search for the keyword "global_reset_n".
  https://www.altera.com/en_US/pdfs/literature/hb/external-memory/emi_ddr_ug.pdf