How do I specify the operating clock when designing an FPGA design with DSP Builder?

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How can I specify the operating clock when designing an FPGA design with DSP Builder?

DSP/Filter Clock/PLL

DSP Builder provides a Clock blockset.
You can set the FPGA's base clock by setting the clock period value for this blockset.

If this blockset is not used, the default of 20ns (50MHz) is set.

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