Are there any settings I can use to reduce FPGA power consumption without changing the design?

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Are there any settings to reduce FPGA power consumption without changing the design?

There is a setting to reduce power consumption, so changing the setting and compiling may reduce power consumption.

Settings in logic synthesis
From the Assignments menu ⇒ Settings
Analysis & Synthesis Settings ⇒ PowerPlay Power Optimization:
Set to Extra effort

Settings in place and route
From the Assignments menu ⇒ Settings
Fitter Settings ⇒ PowerPlay Power Optimization:
Set to Extra effort

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