When I use the Global Clock inside the FPGA as the reference clock for the PLL, a Critical Warning message appears. Is this a problem?

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A Critical Warning is displayed when I use the Global Clock inside the FPGA as the reference clock for the PLL. Will there be any problems?

Quartus Prime Clock/PLL

Since it is recommended to input to the PLL via internal dedicated wiring from dedicated clock pins, a Critical Warning will be displayed in the case of input from Global Clock.

In the case of input from the Global Clock, as mentioned in the Critical Warning message, jitter may be added, which may affect the timing. Input via dedicated internal wiring is recommended.

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