Arria II GX supports differential LVPECL only on input clock pins.
This can be achieved by setting the IO standard of the desired input clock pin to LVDS and providing appropriate external termination.

For details on the external termination method, please refer to the Device Handbook at the URL link below and search for the keyword “Differential LVPECL”.
  https://www.altera.co.jp/en_JP/pdfs/literature/hb/arria-ii-gx/aiigx_51006.pdf

Note that Arria II GX does not support LVPECL output.