Regarding the timing simulation of ModelSim-ALTERA (including Starter) Edition, I would like to set the delay condition to Min. Please tell me how to do this.

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I would like to set the delay condition to Min for the ModelSim-ALTERA (including Starter) Edition timing simulation.

simulation

When simulating with ModelSim-ALTERA, Max and Min can be set on the SDF tab of Start Simulation, but this method cannot reflect them.

When compiling with Quartus II, some SDO files are output, but if it is Min, it can be implemented by using the following files.

For VHDL (* is file name, # is core voltage)
*_min_#mv_0c_fast.vho
*_min_#mv_0c_vhd_fast.sdo

For Verilog HDL (* is file name, # is core voltage)
*_min_#mv_0c_fast.vo
*_min_#mv_0c_vhd_fast.sdo

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