I have written a state machine, but it is not synthesized as a state machine in the compilation report (it is not recognized by State Machine Viewer either). How can I synthesize it as a state machine?

Narrow down by specifying conditions

There are currently 4341 results.

I have described a state machine, but it is not logically synthesized as a state machine on the compilation report (it is not recognized even by the State Machine Viewer). What should I do to synthesize it as a state machine?

Quartus Prime

From the Quartus II menu bar, Assingments ⇒ Settings ⇒ Analysis & Synthesis ⇒ More Settings ⇒ Extract Velilog/VHDL State Machines may be "OFF".

Please set this setting to "ON" and recompile and check the compilation report.

This is an option that detects state machine circuitry in your design and optimizes it as a state machine for less resources and better performance.
If "OFF", the compiler treats the circuit as normal logic and optimizes it.

Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.

Inquiry form

Site Search