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Use Parallel Flash Loader (PFL) with MAX II in FPGA configuration mode. Can the PFL fpga_nconfig output be “H” output?
PFL's fpga_nconfig output is OpenDrain.
This output cannot be changed by design or option settings, so it must be pulled up externally.
For details, please search for the keyword "fpga_nconfig" from the documents in the URL links below.
https://www.altera.com/en_US/pdfs/literature/ug/ug_pfl.pdf (User Guide: English)
https://www.altera.co.jp/ja_JP/pdfs/literature/an/an386_j.pdf (Application Note: Japanese)
https://www.altera.com/en_US/pdfs/literature/an/an386.pdf (Application Note: English)
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