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Can the LVDS Receiver's DPA (Dynamic phase alignment) feature correct skew between channels?

IP Timing Constraint/Analysis

The Bit Slip block in the LVDS Receiver can slip bits for serial data. (Slipped by rx_channel_data_align.)

Bit Slip is for each channel, so it is possible to compensate for channel-to-channel skew of more than 1 UI.
At this time, a separate circuit (a circuit that controls rx_channel_data_align) is required to slip the bits for the serial data using the Bit Slip circuit, such as by sending an alignment pattern.

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