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Use Parallel Flash Loader (PFL) with MAX II in FPGA configuration mode. Are there any recommended settings when designing and implementing PFL?
It is recommended to enable the Safe State Machine setting to prevent the PFL from going into an indeterminate state. Please refer to the PFL IP Core of the application note AN386 at the URL link below for a detailed description of this.
https://www.altera.com/en_US/pdfs/literature/an/an386.pdf
The Quartus II setting method is shown below.
Select Assignments menu ⇒ Settings dialog Box
Click More Settings on the Analysis & Synthesis Settings page
Set this option to ON
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