Can the clock (rx_clkout) recovered from CDR (Clock Data Recovery) in the transceiver block of Stratix IV GX/GT devices be used as the input clock for a general PLL?

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Can the clock (rx_clkout) recovered from CDR (Clock Data Recovery) in the Stratix IV GX/GT device transceiver block be used as the input clock for a general PLL?

Clock/PLL

Can not do.

The input clock of the PLL should be input from another resource (input dedicated pin, output clock from another PLL).

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