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Is it possible to output directly as an LVDS signal from the PLL output?

Clock/PLL IP

Here's how.

  1. Assign signal C0 to PLL*_OUTp (*: number)
  2. Select LVDS for I/O Standard


Compile with the above settings, PLL*_OUT0n will be automatically assigned to allow C0 output to be differential.

supplement:

  • For Cyclone III PLL outputs, C0 is recommended for direct connection to clock output pins. (Recommendations vary by device family, so be sure to check the documentation.)
  • Due to restrictions on placement of input clock pins, output clock pins, and PLLs, always refer to the resource-related information in your device's documentation.

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